PAM-N receiver capable of adaptively adjusting threshold voltages determining level of data in received signal and method of adaptively adjusting threshold voltages of PAM-N receiver

ABSTRACT

A PAM-N receiver capable of adaptively adjusting threshold voltages determining a level of a received signal and a method of adaptively adjusting threshold voltages thereof are disclosed. According to the method of the present invention, the result of comparison between reference data levels and the level of data in the received signal are used to adjust the reference data levels, and the threshold voltages of a PAM-N receiver are adaptively calculated from the adjusted reference data levels, thereby reflecting transmission line conditions and Inter-Symbol Interference.

This non-provisional U.S. patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2021-0176428 filed on Dec. 10, 2021, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

FIELD

The present invention relates to a PAM-N receiver capable of adaptively adjusting threshold voltages determining a level of data in a received signal and a method of adaptively adjusting threshold voltages of a PAM-N receiver.

DESCRIPTION OF THE RELATED ART

Various methods are used in order to transmit digital signals at high speed. While binary data are transmitted conventionally, multi-level pulse amplitude modulation (PAM) has been proposed to transmit digital data at high speed.

FIG. 1A through FIG. 1D are diagrams illustrating waveforms of binary PAM (PAM-2) and multi-level PAM (PAM-4, PAM-8 and PAM-N) signals, respectively.

FIG. 1A illustrates binary data having values ‘0’ and ‘1’. That is, in FIG. 1A, a two-level PAM (PAM-2) signal is illustrated. While PAM-2 signal is robust to noise, PAM-2 has a limitation in increasing signal data rate.

In order to overcome the limitation of PAM-2, PAM-4, PAM-8 and PAM-N have been proposed.

As shown in FIG. 1B, in PAM-4, data having values of ‘00’, ‘01’, ‘10’ and ‘11’ are modulated into a signal with four data levels.

Similarly, as shown in FIG. 1C, in PAM-8, data having values of ‘000’, ‘001’, ‘010’, ‘011’, ‘100’, ‘101’, ‘110’ and ‘111’ are modulated into a signal with eight data levels.

Similarly, as shown in FIG. 1D, in PAM-N, data having values of ‘00 . . . 00’, ‘00 . . . 01’, . . . , ‘11 . . . 11’ are modulated into a signal with N data levels. Here, N is a natural number, and typically, satisfies N=2^(n) (where n is a natural number). If N=2^(n), one pulse contains n bits of data. However, N is not limited to a natural number that satisfies N=2^(n).

As a result, in PAM-4, PAM-8 and PAM-N, data may be transmitted at two, three and n (when N=2^(n)) times faster compared to PAM-2, respectively. However, PAM-4, PAM-8 and PAM-N are more susceptible to attenuation and noise when compared to PAM-2. Therefore, an equalizer capable of equalizing the received signal is necessary in PAM-4, PAM-8 and PAM-N.

FIG. 2 is a block diagram illustrating an equalizer and a sampler of a conventional PAM-N receiver.

Referring to FIG. 2 , the conventional PAM-4 receiver 10 includes an equalizer 20 and a sampler 30.

The equalizer 20 equalizes a received signal RS to generate an equalized signal EQ_(OUT).

The sampler 30 determines the level of the data contained in the output signal EQ_(OUT). For example, a conventional PAM-4 receiver shown in FIG. 2 determines the level of the data contained in the output signal EQ_(OUT) to identify the received data as one of “00”, “01”, “10” and “11”.

FIG. 3A is a diagram schematically illustrating a signal processing process of the conventional PAM-4 receiver 10. As shown in FIG. 3A, assuming that the transmitted signal TS is a digital signal having four data levels “00”, “01”, “10” and “11”, a received signal RS is virtually an analog signal due to the characteristics of the transmission line such as LPF characteristic thereof. While a signal EQ_(OUT) obtained by equalizing the received signal RS is more similar in shape to the transmitted digital signal, the signal EQ_(OUT) still differs from the transmitted signal TS. Therefore, the signal EQ_(OUT) must be converted into a digital signal having four data levels using the sampler 30.

FIG. 3B is a diagram schematically illustrating a process for processing the signal EQ_(OUT) by the sampler 30.

Referring to FIG. 3B, when the level of the data contained in the signal EQ_(OUT) is greater than threshold voltage VTH₃, the sampler 30 determines the data as “11”. When the level of the data contained in the signal EQ_(OUT) is greater than threshold voltage VTH₂ but smaller than VTH₃, the sampler 30 determines the data as “10”. When the level of the data contained in the signal EQ_(OUT) is greater than threshold voltage VTH₁ but smaller than VTH₂, the sampler 30 determines the data as “01”. When the level of the data contained in the signal EQ_(OUT) is smaller than threshold voltage VTH₁, the sampler 30 determines the data as “00”.

However, the problem lies in that the data level of the received signal is subject to change depending on the characteristics of the transmission line.

For example, when a signal TS where the data corresponding to “11” has a data level of 400 mV is transmitted, the level the data corresponding to “11” contained in the received signal RS (or equalized signal EQ_(OUT)) may be 300 mV or 250 mV depending on the characteristics of the transmission line. That is, the amplitude of the transmitted signal TS may differ from that of the received signal RS. However, since these characteristics are not reflected in the threshold voltages VTH₁, VTH₂ and VTH₃ which are the criteria for determining the data level, it is very likely that the data level cannot be accurately determined.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a PAM-N receiver and a method of adaptively adjusting threshold voltages thereof capable of adaptively adjusting threshold voltages for determining levels of data in a received signal.

In order to achieve the object of the present invention, there is provided a method of adjusting threshold voltages of a PAM-N receiver comprising a sampler comparing a level of data contained in an equalized signal EQ_(OUT) with first reference data level DLR₁ through N^(th) reference data level DLR_(N) and first threshold voltage VTH₁ through (N−1)^(th) threshold voltage VTH_((N−1)), the method comprising: (a) determining the level of the data by comparing the level of the data with the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)); (b) comparing the level of the data determined in (a) as K^(th) data level DL_(K) with K^(th) reference data level DLR_(K); (c) increasing the K^(th) reference data level DLR_(K) when DL_(K) is greater than DLR_(K) according to comparison result obtained in (b) and decreasing the K^(th) reference data level DLR_(K) when DL_(K) is smaller than DLR_(K) according to the comparison result obtained in (b) to generate K^(th) updated reference data level DLUR_(K); and (d) updating at least one of (K−1)^(th) threshold voltage VTH_((K−1)) and K^(th) threshold voltage VTH_(K) with (K−1)^(th) updated threshold voltage VUTH_((K−1)) and K^(th) updated threshold voltage VUTH_(K) by calculating at least one of the (K−1)^(th) updated threshold voltage VUTH_((K−1)) and the K^(th) updated threshold voltage VUTH_(K) from the K^(th) updated reference data level DLUR_(K) (where N is a natural number equal to or greater than 2, K is a natural number satisfying 1≤K≤N, DL_(K) is one of DL₁ through DL_(N) satisfying DL₁<DL₂< . . . <DL_((N−1))<DL_(N), DLR_(K) is one of DLR₁ through DLR_(N) satisfying DLR₁<DLR₂< . . . <DLR_((N−1))<DLR_(N), VTH_((K−1)) is one of VTH₁ through VTH_((N−1)) satisfying VTH₁<VTH₂< . . . <VTH_((N−2))<VTH_((N−1))).

It is preferable that the method may further comprise: (e) updating (N−K+1)^(th) threshold voltage VTH_((N−k+1)) with (N−K+1)^(th) updated threshold voltage VUTH_((N−K+1)) obtained by inverting the (K−1)^(th) updated threshold voltage VUTH_((K−1)) when the equalized signal EQ_(OUT) is a differential signal (where, K is a natural number satisfying N/2+1<K≤N).

It is preferable that (d) comprises: (d-1) calculating the (K−1)^(th) updated threshold voltage VUTH_((K−1)) from an average of (K−1)^(th) reference data level DLR_((K−1)) and the K^(th) updated reference data level DLUR_(K); and (d-2) updating the (K−1)^(th) threshold voltage VTH_((K−1)) with the (K−1)^(th) updated threshold voltage VUTH_((K−1)).

It is preferable that (d) comprises: (d-3) calculating the K^(th) updated threshold voltage VUTH_(K) from an average of (K+1)^(th) reference data level DLR_((K+1)) and the K^(th) updated reference data level DLUR_(K); and (d-4) updating the K^(th) threshold voltage VTH_(K) with the K^(th) updated threshold voltage VUTH_(K).

It is preferable that (d) comprises: (d-1) calculating the (K−1)^(th) updated threshold voltage VUTH_((K−1)) from an average of (K−1)^(th) reference data level DLR_((K−1)) and the K^(th) updated reference data level DLUR_(K); (d-2) updating the (K−1)^(th) threshold voltage VTH_((K−1)) with the (K−1)^(th) updated threshold voltage VUTH_((K−1)); (d-3) calculating the K^(th) updated threshold voltage VUTH_(K) from an average of (K+1)^(th) reference data level DLR_((K+1)) and the K^(th) updated reference data level DLUR_(K); and (d-4) updating the K^(th) threshold voltage VTH_(K) with the K^(th) updated threshold voltage VUTH_(K).

It is preferable that the method further comprises: (h) performing, when the received signal contains a plurality of data, (a) through (d) for each of the plurality of data.

There is also provided a PAM-N receiver comprising: an equalizer generating an equalized signal EQ_(OUT) containing data having at least one of first data level DL₁ through N^(th) data level DL_(N) obtained by equalizing a received signal; a sampler determining a level of the data by comparing the level of the data with first reference data level DLR₁ through N^(th) reference data level DLR_(N) and first threshold voltage VTH₁ through (N−1)^(th) threshold voltage VTH_((N−1)); and a controller adjusting the first reference data level DLR₁ through the N^(th) reference data level DLR_(N) and the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)) according to an output signal SMPL_(OUT) indicating a result of comparison performed by the sampler; wherein the sampler comprises a K^(th) data level comparator outputting: “1” as the output signal SMPL_(OUT) when DL_(K) is greater than DLR_(K); and “0” as the output signal SMPL_(OUT) when DL_(K) is smaller than DLR_(K) by comparing the level of the data determined to have K^(th) data level DL_(K) with K^(th) reference data level DLR_(K); and wherein the controller comprises: a reference data level controller generating an K^(th) updated reference data level DLUR_(K) obtained by increasing the K^(th) reference data level DLR_(K) when an output of the K^(th) data level comparator is “1” and by decreasing the K^(th) reference data level DLR_(K) when the output of the K^(th) data level comparator is “0”; and a threshold voltage controller updating at least one of (K−1)^(th) threshold voltage VTH_((K−1)) and K^(th) threshold voltage VTH_(K) with (K−1)^(th) updated threshold voltage VUTH_((K−1)) and K^(th) updated threshold voltage VUTH_(K) by calculating at least one of the (K−1)^(th) updated threshold voltage VUTH_((K−1)) and the K^(th) updated threshold voltage VUTH_(K) from the K^(th) updated reference data level DLUR_(K) (where N is a natural number equal to or greater than 2, K is a natural number satisfying 1≤K≤N, DL_(K) is one of DL₁ through DL_(N) satisfying DL₁<DL₂< . . . <DL_((N−1))<DL_(N), DLR_(K) is one of DLR₁ through DLR_(N) satisfying DLR₁<DLR₂< . . . <DLR_((N−1))<DLR_(N), VTH_((K−1)) is one of VTH₁ through VTH_((N−1)) satisfying VTH₁<VTH₂< . . . <VTH_((N−2))<VTH_((N−1))).

It is preferable that the threshold voltage controller updates (N−K+1)^(th) threshold voltage VTH_((N−K+1)) with (N−K+1)^(th) updated threshold voltage VUTH_((N−K+1)) obtained by inverting the (K−1)^(th) updated threshold voltage VUTH_((K−1)) when the equalized signal EQ_(OUT) is a differential signal (where, K is a natural number satisfying N/2+1<K≤N).

It is preferable that the threshold voltage controller: calculates the (K−1)^(th) updated threshold voltage VUTH_((K−1)) from an average of (K−1)^(th) reference data level DLR_((K−1)) and the K^(th) updated reference data level DLUR_(K); and updates the (K−1)^(th) threshold voltage VTH_((K−1)) with the (K−1)^(th) updated threshold voltage VUTH_((K−1)).

It is preferable that the threshold voltage controller: calculates the K^(th) updated threshold voltage VUTH_(K) from an average of (K+1)^(th) reference data level DLR_((K+1)) and the K^(th) updated reference data level DLUR_(K); and updates the K^(th) threshold voltage VTH_(K) with the K^(th) updated threshold voltage VUTH_(K).

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1D are diagrams illustrating binary PAM (PAM-2) and multi-level PAM (PAM-4, PAM-8 and PAM-N) signals, respectively.

FIG. 2 is a block diagram illustrating an equalizer and a sampler of a conventional PAM-N receiver.

FIG. 3A is a diagram schematically illustrating a signal processing process of the conventional PAM-4 receiver 10 shown in FIG. 2 , and FIG. 3B is a diagram schematically illustrating a process for processing the signal EQ_(OUT) by the sampler 30 of the conventional PAM-4 receiver 10 shown in FIG. 2 .

FIG. 4 is a diagram illustrating a distribution of data levels of a signal RS received by a PAM-4 receiver.

FIG. 5 is a diagram illustrating data level and distribution of a received PAM-N signal and threshold voltages.

FIG. 6 is a block diagram illustrating a PAM-N receiver according to the present invention. FIGS. 7A and 7B are block diagrams illustrating a sampler of a PAM-N receiver according to the present invention.

FIGS. 8A through 8F are block diagrams illustrating a PAM-4 receiver and a sampler according to the present invention.

FIGS. 9A and 9B are diagrams illustrating an increase/decrease of a reference data level according to a data level of a received signal.

FIG. 10 is a flowchart illustrating a method of adaptively adjusting threshold voltages according to an embodiment of the present invention.

FIG. 11 is a flowchart illustrating step S400 in detail.

Hereinafter, a PAM-N receiver and a method of adaptively adjusting threshold voltages thereof capable of adaptively adjusting threshold voltages for determining data levels of a received signal according to the present invention will be described in detail with reference to the accompanying drawings.

First, data levels of a signal RS received by the PAM-N receiver according to the present invention will be described.

FIG. 4 is a diagram illustrating a distribution of data levels of a received signal RS wherein a distribution of data levels of a signal RS received by a PAM-4 receiver is exemplified. While the data levels of the signal RS received by the PAM-4 receiver is exemplified for convenience of description, the signal RS is not limited to ones received by a PAM-4 receiver.

Referring to FIG. 4 , when a PAM-4 transmitter transmits data “11”, the data level of the data “11” received by the PAM-4 receiver should be greater than a threshold voltage VTH₃. Specifically, when the PAM-4 receiver receives a plurality of data “11”, each of the plurality of data “11” may have different data levels due to Inter-Symbol Interference (ISI). The ISI is a phenomenon in which the preceding data affects the following data. For example, when data “00” and “11” are sequentially transmitted and received, the received data “11” is likely to have a relatively low data level, and when data “10” and “11” are sequentially transmitted and received, the received data “11” is likely to have a relatively high data level. Similarly, when data “11” and “00” are sequentially transmitted and received, the received data “00” is likely to have a relatively high data level, and when data “01” and “00” are sequentially transmitted and received, the received data “00” is likely to have a relatively low data level. As a result, even when the same data “11” are repeatedly transmitted, the data levels of the received data “11” differ and distributed throughout a certain range, e.g. follow a distribution DL_(D4) shown in FIG. 4 .

When the PAM-4 transmitter transmits data “10”, the data level of the data “10” received by the PAM-4 receiver should be greater than a threshold voltage VTH₂ and less than the threshold voltage VTH₃. As described above, even when the same data “10” are repeatedly transmitted, the data levels of the received data “10” differ due to ISI and distributed throughout a certain range, e.g. follow a distribution DL_(D3) shown in FIG. 4 .

When the PAM-4 transmitter transmits data “01”, the data level of the data “01” received by the PAM-4 receiver should be greater than a threshold voltage VTH₁ and less than the threshold voltage VTH₂. As described above, even when the same data “01” are repeatedly transmitted, the data levels of the received data “01” differ due to ISI and distributed throughout a certain range, e.g. follow a distribution DL_(D2) shown in FIG. 4 .

When the PAM-4 transmitter transmits data “00”, the data level of the data “00” received by the PAM-4 receiver should be less than the threshold voltage VTH₁. As described above, even when the same data “00” are repeatedly transmitted, the data levels of the received data “00” differ due to ISI and distributed throughout a certain range, e.g. follow a distribution DL_(D1) shown in FIG. 4 .

As described above, even when the same data are repeatedly received, the levels of the actually received data vary within a certain range. That is, even when the same data are repeatedly received, the levels of the received data may be different from one another.

The threshold voltages VTH₁, VTH₂ and VTH₃ shown in FIG. 4 are used to determine the data value of the received signal. For example, when the data level of the received signal is higher than the threshold voltage VTH₃, the value is determined as “11”. Therefore, in order to accurately determine the data value of the received signal, appropriate threshold voltages VTH₁, VTH₂ and VTH₃ are required.

For example, the threshold voltage VTH₃ may be calculated according to equation 1 below where DL₄ denotes any one data level following the distribution DL_(D4) of data “11” shown in FIG. 4 and DL₃ denotes any one data level following the distribution DL_(D3) of data “10”.

$\begin{matrix} {V_{{TH}3} = \frac{{DL}_{4} + {DL}_{3}}{2}} & \left\lbrack {{Equation}1} \right\rbrack \end{matrix}$

Similarly, the threshold voltages VTH₂ and VTH₁ may be calculated according to equations 2 and 3 below, respectively, where DL₂ denotes any one data level following the distribution DL_(D2) of data “01” and DL₁ denotes any one data level following the distribution DL_(D1) of data “00”.

$\begin{matrix} {V_{{TH}2} = \frac{{DL}_{3} + {DL}_{2}}{2}} & \left\lbrack {{Equation}2} \right\rbrack \end{matrix}$ $\begin{matrix} {V_{{TH}1} = \frac{{DL}_{2} + {DL}_{1}}{2}} & \left\lbrack {{Equation}3} \right\rbrack \end{matrix}$

That is, the threshold voltages VTH₁, VTH₂ and VTH₃ may be an average value of two data levels.

However, since the levels of the received data vary within a certain range even when the same data are received, the accuracy of data value determination varies depending on how the threshold voltages VTH₁, VTH₂ and VTH₃ are selected.

Hereinafter, the data levels of the received signal are denoted as DL₁, DL₂, DL₃, . . . and the threshold voltages that actually determine the data value of the received signal are denoted as VTH₁, VTH₂, VTH₃, . . . . A more detailed description are given in the following.

First, as shown in FIG. 5 , each of the levels of a plurality of data included in the signal received by the PAM-N receiver according to the present invention may be any one of N data levels. That is, the signal RS received by the PAM-N receiver includes the plurality of data, and the level of each data may be any one of a first data level DL₁ through an N^(th) data level DL_(N). For example, when data “000 . . . 000” is transmitted and received, the data level corresponding to the received data “000 . . . 000” is the first data level DL₁, and when data “111 . . . 111” is transmitted and received, the data level corresponding to the received data “111 . . . 111” is the N^(th) data level DL_(N). As described above, even when the plurality of data having the same value is repeatedly transmitted, the levels of the received data may differ from one another due to ISI. For example, when a plurality of data “111 . . . 111” is transmitted and received, the received data “111 . . . 111” have a data level of N^(th) data level DL_(N). However, the level of one received data “111 . . . 111” may differ from that of another received data “111 . . . 111” due to ISI. That is, the level of each received data may be an analog value within a certain range. Even when the received signal is equalized by the equalizer, the level of one equalized data “111 . . . 111” may differ from that of another equalized data “111 . . . 111”. Therefore, each of the first data level DL₁ through the N^(th) data level DL_(N) means a certain range as shown in FIG. 4 .

Herein, for example, “the level of the data is the first data level DL₁” means “the level of the data is a voltage within the distribution DL_(D1)”. “The levels of one data and another data are the first data level DL₁” does not necessarily mean “The levels of one data and another data are the same” since the levels of one data and another data are referred to as the first data level DL₁ as long as the levels of one data and another data are both within the same range (distribution DL_(D1)) despite the difference in values due to ISI. That is, each of the first data level DL₁ through the N^(th) data level DL_(N) represents a range rather than a fixed value. For example, when a plurality of data “000 . . . 001” is transmitted and received, the level of each data “000 . . . 001” is “second data level DL₂” as long as the level of each data “000 . . . 001” is within a certain range (distribution DL_(D2)) shown in FIG. 4 . However, the levels of the plurality of data “000 . . . 001” may differ from one another due to ISI.

Herein, in order to facilitate description, any one data level selected from the first data level DL₁ through the N^(th) data level DL_(N) is referred to as a K^(th) data level DL_(K). Here, N is a natural number equal to or greater than 2, and K is a natural number satisfying 1≤K≤N. In addition, the first data level DL₁ through the N^(th) data level DL_(N) satisfies DL₁<DL₂<DL₃< . . . <DL_((N−1))<DL_(N).

In addition, FIG. 5 shows threshold voltages used to determine the data value from the data levels. The data level of the received signal (or equalized signal EQ_(OUT)) is compared with the threshold voltages, and the data value is determined according to the comparison result. For example, when the data level of the received signal is greater than (N−1)^(th) threshold voltage VTH_((N−1)), the data value is determined as “111 . . . 111”, and when the data level of the received signal is smaller than the (N−1)^(th) threshold voltage VTH_((N−1)) but greater than the (N−2)^(th) threshold voltage VTH_((N−2)), the data value is determined as “111 . . . 110”.

Hereinafter, a PAM-N receiver according to the present invention capable of receiving a signal having data levels shown in FIG. 5 will be described in detail.

FIG. 6 is a block diagram illustrating a PAM-N receiver according to the present invention.

Referring to FIG. 6 , a PAM-N receiver 1000 according to the present invention includes an equalizer 100, a sampler 110 and a DEMUX 120.

The equalizer 100 equalizes the received signal RS to generate an output signal EQ_(OUT) having the first data level DL₁ through the N^(th) data level DL_(N).

Specifically, as shown in FIG. 3A or FIG. 3B, the equalized signal EQ_(OUT) is generated by equalizing the received signal RS. The signal EQ_(OUT) includes a plurality of data, and the level of each of plurality of data may be any one of the first data level DL₁ through the N^(th) data level DL_(N).

As described above, even the same transmitted data may have different data levels when received. For example, when the signal EQ_(OUT) contains two received data both corresponding to data “111 . . . 111”, the data levels of the first received data “111 . . . 111” and the second received data “111 . . . 111” may be different. However, when the level of the first received data “111 . . . 111” and the level of the second received data “111. . . . 111” are both in a certain range greater than the (N−1)^(th) threshold voltage VTH_((N−1)), both the first received data and the second received data may be collectively referred to as having the N^(th) data level DL_(N).

That is, when the signal EQ_(OUT) contains at least one data, each level of the at least one data included in the signal EQ_(OUT) may is one of the first data level DL₁ through the N^(th) data level DL_(N).

The sampler 110 samples the output signal EQ_(OUT) according to a first reference data level DLR₁ through an N^(th) reference data level DLR_(N) and the first threshold voltage VTH₁ to the (N−1)^(th) threshold voltage VTH_((N−1)).

Specifically, the sampler 110 compares the level of each data included in the signal EQ_(OUT) with the first reference data level DLR₁ through the N^(th) reference data level DLR_(N), and with the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)), and outputs an output signal SMPL_(OUT) which represents the comparison result.

Here, the reference data levels are reference voltages used in the comparison with the level of the received signal (or the equalized signal EQ_(OUT)). As described above, the data levels of the received signal (or the equalized signal EQ_(OUT)) may differ from one another even for the same transmitted data. That is, due to factors affecting data transmission such as noise and/or ISI, even the data level for the same transmitted data may differ for each reception. Therefore, it is essential to select or adjust the threshold voltages reflecting the characteristics affecting data transmission and ISI in order to determine the data level accurately. In accordance with the present invention, predetermined reference data levels are first selected (“initial reference data levels”) and the threshold voltages appropriate for determining the level of the received signal (or equalized signal EQ_(OUT)) are then calculated by increasing or decreasing the reference data level depending on which one of the level of the received signal (or equalized signal EQ_(OUT)) and the reference data level is greater. While the initial reference data levels maybe arbitrarily selected, it is preferable that the average value of the initial threshold voltage be set as the initial reference data level. For example, in FIG. 5 , the average of the (N−1)^(th) threshold voltage VTH_((N−1)) and the (N−2)^(th) threshold voltage VTH_((N−2)) may be selected as a reference data level DLR_((N−1)). Alternatively, a data level corresponding to an average value (a data level that occurs most frequently) in the distribution of the received signal (or equalized signal EQ_(OUT)) may be selected as the reference data level. Regardless of how the initial reference data levels are chosen, the threshold voltages eventually converge to optimal values as data are received since the reference data level is increased or decreased according to the level of the received signal.

The DEMUX 120 parallelizes the output signal SMPL_(OUT) of the sampler 110 and outputs parallelized signal as signal DATA_(OUT). That is, the output signal SMPL_(OUT) is de-serialized and provided to the controller 130 as the signal DATA_(OUT).

Hereinafter, the sampler 110 will be described in detail with reference to FIGS. 7A and 7B.

FIG. 7A is a block diagram illustrating the sampler 110 including a plurality of comparators.

Referring to FIG. 7A, the sampler 110 includes first threshold voltage comparator 112-1 through (N−1)^(th) threshold voltage comparator 112-(N−1) and first data level comparator 114-1 through N^(th) data level comparator 114-N (where N is a natural number).

The first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1) compare the level of each data included in the signal EQ_(OUT) with the first threshold voltage VTH₁ to the (N−1)^(th) threshold voltage VTH_((N−1)), and output the comparison result.

For example, the first threshold voltage comparator 112-1 compares the signal EQ_(OUT) with the first threshold voltage VTH₁ for each clock CLK and outputs a signal THCP₁ representing a comparison result. That is, the first threshold voltage comparator 112-1 outputs THCP₁=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the first threshold voltage VTH₁, and outputs THCP₁=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the first threshold voltage VTH₁.

The second threshold voltage comparator 112-2 compares the signal EQ_(OUT) with the second threshold voltage VTH₂ for each clock CLK and outputs a signal THCP₂ representing a comparison result. That is, the second threshold voltage comparator 112-2 outputs THCP₂=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the second threshold voltage VTH₂, and outputs THCP₂=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the second threshold voltage VTH₂.

Similarly, the (N−2)^(th) threshold voltage comparator 112-(N−2) compares the signal EQ_(OUT) with the (N−2)^(th) threshold voltage VTH_((N−2)) for each clock CLK and outputs a signal THCP_((N−2)) representing a comparison result. That is, the (N−2)^(th) threshold voltage comparator 112-(N−2) outputs THCP_((N−2))=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the (N−2)^(th) threshold voltage VTH_((N−2)), and outputs THCP_((N−2))=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the (N−2)^(th) threshold voltage VTH_((N−2)).

Similarly, the (N−1)^(th) threshold voltage comparator 112-(N−1) compares the signal EQ_(OUT) with the (N−1)^(th) threshold voltage VTH_((N−1)) for each clock CLK and outputs a signal THCP_((N−1)) representing a comparison result. That is, the (N−1)^(th) threshold voltage comparator 112-(N−1) outputs THCP_((N−1))=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the (N−1)^(th) threshold voltage VTH_((N−1)), and outputs THCP_((N−1))=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the (N−1)^(th) threshold voltage VTH_((N−1)).

A K^(th) threshold voltage comparator 112-K (where “K^(th) threshold voltage comparator 112-K” represents any one of the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1)) outputs a signal THCP_(K) representing a comparison result obtained by comparing the signal EQ_(OUT) with the K^(th) threshold voltage VTH_(K) for each clock CLK. Specifically, the K^(th) threshold voltage comparator 112-K outputs THCP_(K)=1 when the level of the data included in the signal EQ_(OUT) is greater than the K^(th) threshold voltage VTH_(K), and outputs THCP_(K)=0 when the level of the data included in the signal EQ_(OUT) is smaller than the K^(th) threshold voltage VTH_(K).

A (K−1)^(th) threshold voltage comparator 112-(K−1), which is adjacent to the K^(th) threshold voltage comparator 112-K, outputs a signal THCP_((K−1)) representing a comparison result obtained by comparing the signal EQ_(OUT) with the (K−1)^(th) threshold voltage VTH_((K−1)) for each clock CLK. Specifically, the (K−1)^(th) threshold voltage comparator 112-(K−1) outputs THCP_((K−1))=1 when the level of the data included in the signal EQ_(OUT) is greater than the (K−1)^(th) threshold voltage VTH_((K−1)), and outputs THCP_((K−1))=0 when the level of the data included in the signal EQ_(OUT) is smaller than the (K−1)^(th) threshold voltage VTH_((K−1)).

Here, K is a natural number satisfying 1≤K≤(N−1), and VTH₁, VTH₂, VTH₃, . . . , VTH_((N−2)) and VTH_((N−1)) satisfy VTH₁<VTH₂<VTH₃< . . . <VTH_((N−2))<VTH_((N−1)).

The level of the data contained in the signal EQ_(OUT) is determined from the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively. For example, when the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, are all “1”, the level of the data included in the signal EQ_(OUT) is determined as the N^(th) data level DL_(N), and when the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, are all “0”, the level of the data included in the signal EQ_(OUT) is determined as the first data level DL₁.

This may be applied to the (K−1)^(th) threshold voltage comparator 112-(K−1). For example, when the signal THCP₁ through the signal THCP_((K−1)) outputted by the first threshold voltage comparator 112-1 through the (K−1)^(th) threshold voltage comparator 112-(K−1), respectively, are all “1”, and the signal THCP_(K) through the signal THCP_((N−1)) outputted by the K^(th) threshold voltage comparator 112-K through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, are all “0”, the level of the data included in the signal EQ_(OUT) is determined as the K^(th) data level DL_(K). That is, when THCP₁=THCP₂= . . . =THCP_((K−1))=1 and, THCP_(K)=THCP_((K+1))= . . . =THCP_((N−1))=0, the level of the data included in the signal EQ_(OUT) is the K^(th) data level DL_(K). Therefore, the level of the data included in the signal EQ_(OUT) may be determined by checking the values outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1).

The first data level comparator 114-1 through the N^(th) data level comparator 114-N compare the level of the data included in the signal EQ_(OUT) with the first reference data level DLR₁ through the N^(th) reference data level DLR_(N), respectively, and output the comparison result thereof.

For example, the first data level comparator 114-1 compares the signal EQ_(OUT) with the first reference data level DLR₁ for each clock CLK, and outputs a signal DLCP₁ representing the comparison result. Specifically, the first data level comparator 114-1 outputs DLCP₁=1 when the level of the data included in the signal EQ_(OUT) is greater than the first reference data level DLR₁, and outputs DLCP₁=0 when the level of the data included in the signal EQ_(OUT) is smaller than the first reference data level DLR₁.

The second data level comparator 114-2 compares the signal EQ_(OUT) with the second reference data level DLR₂ for each clock CLK, and outputs a signal DLCP₂ representing the comparison result. Specifically, the second data level comparator 114-2 outputs DLCP₂=1 when the level of the data included in the signal EQ_(OUT) is greater than the second reference data level DLR₂, and outputs DLCP₂=0 when the level of the data included in the signal EQ_(OUT) is smaller than the second reference data level DLR₂.

The (N−1)^(th) data level comparator 114-(N−1) compares the signal EQ_(OUT) with the (N−1)^(th) reference data level DLR_((N−1)) for each clock CLK, and outputs a signal DLCP_((N−1)) representing the comparison result. Specifically, the (N−1)^(th) data level comparator 114-(N−1) outputs DLCP_((N−1))=1 when the level of the data included in the signal EQ_(OUT) is greater than the (N−1)^(th) reference data level DLR_((N−1)), and outputs DLCP_((N−1))=0 when the level of the data included in the signal EQ_(OUT) is smaller than the (N−1)^(th) reference data level DLR_((N−1)).

The N^(th) data level comparator 114-N compares the signal EQ_(OUT) with the N^(th) reference data level DLR_(N) for each clock CLK, and outputs a signal DLCP_(N) representing the comparison result. Specifically, the N^(th) data level comparator 114-N outputs DLCP_(N)=1 when the level of the data included in the signal EQ_(OUT) is greater than the N^(th) reference data level DLR_(N), and outputs DLCP_(N)=0 when the level of the data included in the signal EQ_(OUT) is smaller than the N^(th) reference data level DLR_(N).

A K^(th) data level comparator 114-K (where “K^(th) data level comparator 114-K” represents any one of the first data level comparator 114-1 through the N^(th) data level comparator 114-N) outputs a signal DLCP_(K) representing a comparison result obtained by comparing the signal EQ_(OUT) with the K^(th) reference data level DLR_(K) for each clock CLK. Specifically, the K^(th) data level comparator 114-K outputs DLCP_(K)=1 when the level of the data included in the signal EQ_(OUT) is greater than the K^(th) reference data level DLR_(K), and outputs DLCP_(K)=0 when the level of the data included in the signal EQ_(OUT) is smaller than the K^(th) reference data level DLR_(K).

A (K−1)^(th) data level comparator 114-(K−1), which is adjacent to the K^(th) data level comparator 114-K, outputs a signal DLCP_((K−1)) representing a comparison result obtained by comparing the signal EQ_(OUT) with the (K−1)^(th) reference data level DLR_((K−1)) for each clock CLK. Specifically, the (K−1)^(th) data level comparator 114-(K−1) outputs DLCP_((K−1))=1 when the level of the data included in the signal EQ_(OUT) is greater than the (K−1)^(th) reference data level DLR_((K−1)), and outputs DLCP_((K−1))=0 when the level of the data included in the signal EQ_(OUT) is smaller than the (K−1)^(th) reference data level DLR_((K−1)).

Here, K is a natural number satisfying 1≤K≤N, and DLR₁, DLR₂, DLR₃, . . . , DLR_((N−1)), and DLR_(N) satisfy DLR₁<DLR₂<DLR₃< . . . <DLR_((N−1))<DLR_(N). In other words, each of the first data level comparator 114-1 through the N^(th) data level comparator 114-N compare the level of the data included in the signal EQ_(OUT) with the corresponding reference data level thereof.

The signal DLCP₁ through the signal DLCP_(N) outputted by the first data level comparator 114-1 through the N^(th) data level comparator 114-N, respectively, are used to determined which one of the level of the data included in the signal EQ_(OUT) and the reference data level is greater. For example, when the data included in the signal EQ_(OUT) is determined to have a level of the N^(th) data level DL_(N) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(N) outputted by the N^(th) data level comparator 114-N is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the N^(th) reference data level DLR_(N). Similarly, when the data included in the signal EQ_(OUT) is determined to have a level of the first data level DL₁ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₁ outputted by the first data level comparator 114-1 is “0”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be smaller than the first reference data level DLR₁.

This may be applied to the K^(th) data level comparator 114-K as follows.

When the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted by the K^(th) data level comparator 114-K is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the K^(th) reference data level DLR_(K).

In addition, when the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted by the K^(th) data level comparator 114-K is “0”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be smaller than the K^(th) reference data level DLR_(K).

The sampler 110 outputs an output signal SMPL_(OUT) which contains the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, and the signal DLCP₁ through the signal DLCP_(N) outputted by the first data level comparator 114-1 through the N^(th) data level comparator 114-N, respectively.

The output signal SMPL_(OUT) is transmitted to the controller 130 via the DEMUX 120 as a signal DATA_(OUT).

FIG. 7B is a block diagram illustrating the sampler 110 including a plurality of comparators wherein an updated threshold voltage and an updated reference data level are applied to the plurality of comparators illustrated in FIG. 7A is exemplified.

Referring to FIG. 7B, the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1) compare the level of the data included in the signal EQ_(OUT) with an first updated threshold voltage VUTH₁ through an (N−1)^(th) updated threshold voltage VUTH_((N−1)), and output the comparison result.

For example, the first threshold voltage comparator 112-1 compares the signal EQ_(OUT) with the first updated threshold voltage VUTH₁ for each clock CLK and outputs a signal THCP₁ representing a comparison result. That is, the first threshold voltage comparator 112-1 outputs THCP₁=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the first updated threshold voltage VUTH₁, and outputs THCP₁=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the first updated threshold voltage VUTH₁.

The second threshold voltage comparator 112-2 compares the signal EQ_(OUT) with the second updated threshold voltage VUTH₂ for each clock CLK and outputs a signal THCP₂ representing a comparison result. That is, the second threshold voltage comparator 112-2 outputs THCP₂=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the second updated threshold voltage VUTH₂, and outputs THCP₂=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the second updated threshold voltage VUTH₂.

The (N−2)^(th) threshold voltage comparator 112-(N−2) compares the signal EQ_(OUT) with the (N−2)^(th) updated threshold voltage VUTH_((N−2)) for each clock CLK and outputs a signal THCP_((N−2)) representing a comparison result. That is, the (N−2)^(th) threshold voltage comparator 112-(N−2) outputs THCP_((N−2))=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the (N−2)^(th) updated threshold voltage VUTH_((N−2)), and outputs THCP_((N−2))=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the (N−2)^(th) updated threshold voltage VUTH_((N−2)).

Similarly, the (N−1)^(th) threshold voltage comparator 112-(N−1) compares the signal EQ_(OUT) with the (N−1)^(th) updated threshold voltage VUTH_((N−1)) for each clock CLK and outputs a signal THCP_((N−1)) representing a comparison result. That is, the (N−1)^(th) threshold voltage comparator 112-(N−1) outputs THCP_((N−1))=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the (N−1)^(th) updated threshold voltage VUTH_((N−1)), and outputs THCP_((N−1))=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the (N−1)^(th) updated threshold voltage VUTH_((N−1)).

The K^(th) threshold voltage comparator 112-K (where “K^(th) threshold voltage comparator 112-K” represents any one of the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1)) outputs a signal THCP_(K) representing a comparison result obtained by comparing the signal EQ_(OUT) with the K^(th) updated threshold voltage VUTH_(K) for each clock CLK. Specifically, the K^(th) threshold voltage comparator 112-K outputs THCP_(K)=1 when the level of the data included in the signal EQ_(OUT) is greater than the K^(th) updated threshold voltage VUTH_(K), and outputs THCP_(K)=0 when the level of the data included in the signal EQ_(OUT) is smaller than the K^(th) updated threshold voltage VUTH_(K).

The (K−1)^(th) threshold voltage comparator 112-(K−1), which is adjacent to the K^(th) threshold voltage comparator 112-K, outputs a signal THCP_((K−1)) representing a comparison result obtained by comparing the signal EQ_(OUT) with the (K−1)^(th) updated threshold voltage VUTH_((K−1)) for each clock CLK. Specifically, the (K−1)^(th) threshold voltage comparator 112-(K−1) outputs THCP_((K−1))=1 when the level of the data included in the signal EQ_(OUT) is greater than the (K−1)^(th) updated threshold voltage VUTH_((K−1)), and outputs THCP_((K−1))=0 when the level of the data included in the signal EQ_(OUT) is smaller than the (K−1)^(th) updated threshold voltage VUTH_((K−1)).

Here, K is a natural number satisfying 1≤K≤(N−1), and VTH₁, VTH₂, VTH₃, . . . , VTH_((N−2)) and VTH_((N−1)) satisfy VTH₁<VTH₂<VTH₃< . . . <VTH_((N−2))<VTH_((N−1)).

The level of the data contained in the signal EQ_(OUT) is determined from the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively. For example, when the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, are all “1”, the level of the data included in the signal EQ_(OUT) is determined as the N^(th) data level DL_(N), and when the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, are all “0”, the level of the data included in the signal EQ_(OUT) is determined as the first data level DL₁.

This may be applied to the (K−1)^(th) threshold voltage comparator 112-(K−1). For example, when the signal THCP₁ through the signal THCP_((K−1)) outputted by the first threshold voltage comparator 112-1 through the (K−1)^(th) threshold voltage comparator 112-(K−1), respectively, are all “1”, and the signal THCP_(K) through the signal THCP_((N−1)) outputted by the K^(th) threshold voltage comparator 112-K through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, are all “0”, the level of the data included in the signal EQ_(OUT) is determined as the K^(th) data level DL_(K). That is, when THCP₁=THCP₂= . . . =THCP_((K−1))=1 and, THCP_(K)=THCP_((K+1))= . . . =THCP_((N−1))=0, the level of the data included in the signal EQ_(OUT) is the K^(th) data level DL_(K). Therefore, the level of the data included in the signal EQ_(OUT) may be determined by checking the values outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1).

The first data level comparator 114-1 through the N^(th) data level comparator 114-N compare the level of the data included in the signal EQ_(OUT) with the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N), respectively, and output the comparison result thereof.

For example, the first data level comparator 114-1 compares the signal EQ_(OUT) with the first updated reference data level DLUR₁ for each clock CLK, and outputs a signal DLCP₁ representing the comparison result. Specifically, the first data level comparator 114-1 outputs DLCP₁=1 when the level of the data included in the signal EQ_(OUT) is greater than the first updated reference data level DLUR₁, and outputs DLCP₁=0 when the level of the data included in the signal EQ_(OUT) is smaller than the first updated reference data level DLUR₁.

The second data level comparator 114-2 compares the signal EQ_(OUT) with the second updated reference data level DLUR₂ for each clock CLK, and outputs a signal DLCP₂ representing the comparison result. Specifically, the second data level comparator 114-2 outputs DLCP₂=1 when the level of the data included in the signal EQ_(OUT) is greater than the second updated reference data level DLUR₂, and outputs DLCP₂=0 when the level of the data included in the signal EQ_(OUT) is smaller than the second updated reference data level DLUR₂.

The (N−1)^(th) data level comparator 114-(N−1) compares the signal EQ_(OUT) with the (N−1)^(th) updated reference data level DLUR(N-I) for each clock CLK, and outputs a signal DLCP_((N−1)) representing the comparison result. Specifically, the (N−1)^(th) data level comparator 114-(N−1) outputs DLCP_((N−1))=1 when the level of the data included in the signal EQ_(OUT) is greater than the (N−1)^(th) updated reference data level DLUR_((N−1)), and outputs DLCP_((N−1))=0 when the level of the data included in the signal EQ_(OUT) is smaller than the (N−1)^(th) updated reference data level DLUR_((N−1)).

The N^(th) data level comparator 114-N compares the signal EQ_(OUT) with the N^(th) updated reference data level DLUR_(N) for each clock CLK, and outputs a signal DLCP_(N) representing the comparison result. Specifically, the N^(th) data level comparator 114-N outputs DLCP_(N)=1 when the level of the data included in the signal EQ_(OUT) is greater than the N^(th) updated reference data level DLUR_(N), and outputs DLCP_(N)=0 when the level of the data included in the signal EQ_(OUT) is smaller than the N^(th) updated reference data level DLUR_(N).

The K^(th) data level comparator 114-K (where “K^(th) data level comparator 114-K” represents any one of the first data level comparator 114-1 through the N^(th) data level comparator 114-N) outputs a signal DLCP_(K) representing a comparison result obtained by comparing the signal EQ_(OUT) with the K^(th) updated reference data level DLUR_(K) for each clock CLK. Specifically, the K^(th) data level comparator 114-K outputs DLCP_(K)=1 when the level of the data included in the signal EQ_(OUT) is greater than the K^(th) updated reference data level DLUR_(K), and outputs DLCP_(K)=0 when the level of the data included in the signal EQ_(OUT) is smaller than the K^(th) updated reference data level DLUR_(K).

The (K−1)^(th) data level comparator 114-(K−1), which is adjacent to the K^(th) data level comparator 114-K, outputs a signal DLCP_((K−1)) representing a comparison result obtained by comparing the signal EQ_(OUT) with the (K−1)^(th) updated reference data level DLUR_((K−1)) for each clock CLK. Specifically, the (K−1)^(th) data level comparator 114-(K−1) outputs DLCP_((K−1))=1 when the level of the data included in the signal EQ_(OUT) is greater than the (K−1)^(th) updated reference data level DLUR_((K−1)), and outputs DLCP_((K−1))=0 when the level of the data included in the signal EQ_(OUT) is smaller than the (K−1)^(th) updated reference data level DLUR_((K−1)).

Here, K is a natural number satisfying 1≤K≤N, and DLUR₁, DLUR₂, DLUR₃, . . . , DLUR_((N−1)), and DLUR_(N) satisfy DLUR₁<DLUR₂<DLUR₃< . . . <DLUR_((N−1))<DLUR_(N). In other words, each of the first data level comparator 114-1 through the N^(th) data level comparator 114-N compare the level of the data included in the signal EQ_(OUT) with the corresponding updated reference data level thereof.

The signal DLCP₁ through the signal DLCP_(N) outputted by the first data level comparator 114-1 through the N^(th) data level comparator 114-N, respectively, are used to determined which one of the level of the data included in the signal EQ_(OUT) and the updated reference data level is greater. For example, when the data included in the signal EQ_(OUT) is determined to have a level of the N^(th) data level DL_(N) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(N) outputted by the N^(th) data level comparator 114-N is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the N^(th) updated reference data level DLUR_(N). Similarly, when the data included in the signal EQ_(OUT) is determined to have a level of the first data level DL₁ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₁ outputted by the first data level comparator 114-1 is “0”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be smaller than the first updated reference data level DLUR₁.

This may be applied to the K^(th) data level comparator 114-K as follows.

When the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted by the K^(th) data level comparator 114-K is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the K^(th) updated reference data level DLUR_(K).

In addition, when the level of the data included in the signal EQ_(OUT) is determined to be the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted by the K^(th) data level comparator 114-K is “0”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be smaller than the K^(th) updated reference data level DLUR_(K).

The sampler 110 outputs an output signal SMPL_(OUT) which contains the signal THCP₁ through the signal THCP_((N−1)) outputted by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), respectively, and the signal DLCP₁ through the signal DLCP_(N) outputted by the first data level comparator 114-1 through the N^(th) data level comparator 114-N, respectively.

The output signal SMPL_(OUT) is transmitted to the controller 130 via the DEMUX 120 as a signal DATA_(OUT).

The controller 130 adjusts the first reference data level DLR₁ through the N^(th) reference data level DLR_(N) and the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)) according to the output signal SMPL_(OUT) of the sampler 110

Specifically, as shown in FIG. 6 , the controller 130 includes a threshold voltage controller 132 and a reference data level controller 134.

The reference data level controller 134 adjusts the first reference data level DLR₁ through the N^(th) reference data level DLR_(N) according to the signal DLCP₁ to the signal DLCP_(N) outputted by the first data level comparator 114-1 through the N^(th) data level comparator 114-N, respectively and included in the output signal SMPL_(OUT).

More specifically, for example, when the data included in the signal EQ_(OUT) is determined to have a level of the first data level DL₁ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₁ outputted from the first data level comparator 114-1 is “1”, the reference data level controller 134 increases the first reference data level DLR₁ by a predetermined value to generate the first updated reference data level DLUR₁.

Contrarily, when the data included in the signal EQ_(OUT) is determined to have a level of the first data level DL₁ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₁ outputted from the first data level comparator 114-1 is “0”, the reference data level controller 134 decreases the first reference data level DLR₁ by a predetermined value to generate the first updated reference data level DLUR₁.

Similarly, for example, when the data included in the signal EQ_(OUT) is determined to have a level of the second data level DL₂ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₂ outputted from the second data level comparator 114-2 is “1”, the reference data level controller 134 increases the second reference data level DLR₂ by a predetermined value to generate the second updated reference data level DLUR₂.

Contrarily, when the data included in the signal EQ_(OUT) is determined to have a level of the second data level DL₂ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₂ outputted from the second data level comparator 114-2 is “0”, the reference data level controller 134 decreases the second reference data level DLR₂ by a predetermined value to generate the second updated reference data level DLUR₂.

As another example, when the data included in the signal EQ_(OUT) is determined to have a level of the third data level DL₃ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₃ outputted from the third data level comparator 114-3 is “1”, the reference data level controller 134 increases the third reference data level DLR₃ by a predetermined value to generate the third updated reference data level DLUR₃.

Contrarily, when the data included in the signal EQ_(OUT) is determined to have a level of the third data level DL₃ by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP₃ outputted from the third data level comparator 114-3 is “0”, the reference data level controller 134 decreases the third reference data level DLR₃ by a predetermined value to generate the third updated reference data level DLUR₃.

This may be applied to the K^(th) data level comparator 114-K described above. For example, when the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted from the K^(th) data level comparator 114-K is “1” (that is, when DL_(K)>DLR_(K) as shown in FIG. 9A), the reference data level controller 134 increases the K^(th) reference data level DLR_(K) by a predetermined voltage to generate the K^(th) updated reference data level DLUR_(K).

In addition, as another example, when the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted from the K^(th) data level comparator 114-K is “0” (that is, when DL_(K)<DLR_(K) as shown in FIG. 9B), the reference data level controller 134 decreases the K^(th) reference data level DLR_(K) by a predetermined voltage to generate the K^(th) updated reference data level DLUR_(K).

The reference data level controller 134 provides the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) to the sampler 110.

The sampler 110 compares the received signal RS (or equalized signal EQ_(OUT)) with the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) and to determine which one of the received signal RS (or equalized signal EQ_(OUT)) and the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) is greater, and provides the comparison result to the controller 130. That is, the sampler 110 updates the first reference data level DLR₁ through the N^(th) reference data level DLR_(N) with the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N), and each data included in the received signal RS (or equalized signal EQ_(OUT)) is subjected to the process described above.

The threshold voltage controller 132 calculates at least one of a (K−1)^(th) updated threshold voltage VUTH_((K−1)) and a K^(th) updated threshold voltage VUTH_(K) from the K^(th) updated reference data level DLUR_(K), and updates at least one of the (K−1)^(th) threshold voltage VTH_((K−1)) and the K^(th) threshold voltage VTH_(K) of the sampler 110 with the calculated (K−1)^(th) updated threshold voltage VUTH_((K−1)) and the calculated K^(th) updated threshold voltage VUTH_(K).

According to one embodiment of the present invention, the threshold voltage controller 132 generates the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)) from the first reference data level DLR₁ through N^(th) reference data level DLR_(N) and the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) generated by the reference data level controller 134, thereby updating each threshold voltage of the sampler 110.

For example, as shown in equation 4 below, the threshold voltage controller 132 may update the (K−1)^(th) threshold voltage VTH_((K−1)) with the (K−1)^(th) updated threshold voltage VUTH_((K−1)) obtained from the average of the K^(th) updated reference data level DLUR_(K) and the (K−1)^(th) reference data level DLR_((K−1)). That is, the threshold voltage controller 132 may update two neighboring threshold voltages from the K^(th) updated reference data level DLUR_(K).

$\begin{matrix} {{VUTH}_{({K - 1})} = \frac{{DLUR}_{K} + {DLR}_{({K - 1})}}{2}} & \left\lbrack {{Equation}4} \right\rbrack \end{matrix}$

In another embodiment, as shown in equation 5 below, the threshold voltage controller 132 may update the K^(th) threshold voltage VTH_(K) with the K^(th) updated threshold voltage VUTH_(K) obtained from the average of the (K+1)^(th) reference data level DLR_((K+1)) and the K^(th) updated reference data level DLUR_(K).

$\begin{matrix} {{VUTH}_{K} = \frac{{DLR}_{({K + 1})} + {DLUR}_{K}}{2}} & \left\lbrack {{Equation}5} \right\rbrack \end{matrix}$

The threshold voltage controller 132 may update only the (K−1)^(th) threshold voltage VTH_((K−1)), update only the K^(th) threshold voltage VTH_(K), or update both of the (K−1)^(th) threshold voltage VTH_((K−1)) and the K^(th) threshold voltage VTH_(K). That is, The threshold voltage controller 132 may update either the (K−1)^(th) threshold voltage VTH_((K−1))or the K^(th) threshold voltage VTH_(K), or both of the (K−1)^(th) threshold voltage VTH_((K−1)) and the K^(th) threshold voltage VTH_(K) from the K^(th) updated reference data level DLUR_(K) which is generated when there is a change in the K^(th) reference data level DLR_(K). However, when the first reference data level DLR₁ is adjusted to generate the first updated reference data level DLUR₁, only the first threshold voltage VTH₁ is updated, and when the N^(th) reference data level DLR_(N) is adjusted to generate the N^(th) updated reference data level DLUR_(N), only the (N−1)^(th) threshold voltage VTH_((N−1)) is updated.

Here, “update” means to replace the old value with a new value. For example, “to update the K^(th) threshold voltage VTH_(K) with the K^(th) updated threshold voltage VUTH_(K)” means that “the value of the K^(th) threshold voltage VTH_(K) is replaced with that of the K^(th) updated threshold voltage VUTH_(K)” or “the value of the K^(th) threshold voltage VTH_(K) is overwritten by that of the K^(th) updated threshold voltage VUTH_(K).”

The threshold voltage controller 132 provides the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)) to the sampler 110.

The sampler 110 may update the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)) with the first threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)), respectively, and compare the updated threshold voltage with the level of the data.

That is, as shown in FIG. 7B, the sampler 110 compares the data included in the output signal EQ_(OUT) with the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) and the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)) provided by the controller 130, and provides the comparison result as the output signal SMPL_(OUT) to the controller 130. While FIG. 7B shows the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) and the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)), the entirety of the first updated reference data level DLUR₁ through the N^(th) updated reference data level DLUR_(N) and the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)) may or may not be updated. For example, only the first reference data level DLR₁ may be updated with the first updated reference data level DLUR₁ depending on the level of the output signal EQ_(OUT). Similarly, only the second threshold voltage VTH₂ and the fourth threshold voltage VTH₄ may be updated with second updated threshold voltage VUTH₂ and the fourth updated threshold voltage VUTH₄, respectively, depending on the level of the output signal EQ_(OUT). In other words, when the reference data level controller 134 and the threshold voltage controller 132 generate any updated reference data levels and updated threshold voltages, the updated reference data levels and the updated threshold voltages are provided to the sampler 110 and the reference data levels and the threshold voltages of the sampler 110 are replaced with the updated reference data levels and the updated threshold voltages, respectively. A detailed description will be given with reference to FIG. 8A through FIG. 8E later.

According to another embodiment of the present invention, when the received signal RS or equalized signal EQ_(OUT) is a differential signal, all of the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)) are not required to be calculated. Specifically, since the differential signal includes a differential pair consisting of non-inverted and inverted signals, a threshold voltage for the non-inverted signal may be inverted to obtain a threshold voltage for the inverted signal.

That is, when the received signal RS or equalized signal EQ_(OUT) is a differential signal, the threshold voltage controller 132 may invert the (K−1)^(th) updated threshold voltage VUTH_((K−1)) to generate the (N−K+1)^(th) updated threshold voltage VUTH_((N−K+1)), and both of the (K−1)^(th) updated threshold voltage VUTH_((K−1)) and the (N−K+1)^(th) updated threshold voltage VUTH_((N−K+1)) may be provided to the sampler 110.

To facilitate the understanding of the present invention, an example receiver according to the present invention capable of receiving a PAM-4 signal will be described with reference to FIGS. 8A through 8F.

FIG. 8A is a block diagram illustrating a PAM-4 receiver 1000 a according to the present invention. The PAM-4 receiver 1000 a according to the present invention shown in FIG. 8A is identical to the PAM-N receiver 1000 shown in FIG. 6 except the configuration of a sampler 110 a and the signals provided to the controller 130. Therefore, the PAM-4 receiver 1000 a according to the present invention will be described with a focus on the configuration of the sampler 110 a and the signals exchanged between the sampler 110 a and the controller 130 hereinafter.

FIG. 8B is a diagram illustrating the sampler 110 a capable of sampling a PAM-4 signal. That is, the sampler 110 a shown in FIG. 8B is the same as the sampler 110 shown in FIG. 7A when N=4.

Referring to FIG. 8B, the sampler 110 a includes a first threshold voltage comparator 112-1 through a third threshold voltage comparator 112-3 and a first data level comparator 114-1 through a fourth data level comparator 114-4.

The first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 compare the level of each data included in the signal EQ_(OUT) with the first threshold voltage VTH₁ to the third threshold voltage VTH₃, and output the comparison result.

For example, the first threshold voltage comparator 112-1 compares the signal EQ_(OUT) with the first threshold voltage VTH₁ for each clock CLK and outputs a signal THCP₁ representing a comparison result. That is, the first threshold voltage comparator 112-1 outputs THCP₁=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the first threshold voltage VTH₁, and outputs THCP₁=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the first threshold voltage VTH₁.

The second threshold voltage comparator 112-2 compares the signal EQ_(OUT) with the second threshold voltage VTH₂ for each clock CLK and outputs a signal THCP₂ representing a comparison result. That is, the second threshold voltage comparator 112-2 outputs THCP₂=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the second threshold voltage VTH₂, and outputs THCP₂=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the second threshold voltage VTH₂.

The third threshold voltage comparator 112-3 compares the signal EQ_(OUT) with the third threshold voltage VTH₃ for each clock CLK and outputs a signal THCP₃ representing a comparison result. That is, the third threshold voltage comparator 112-3 outputs THCP₃=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the third threshold voltage VTH₃, and outputs THCP₃=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the third threshold voltage VTH₃.

The level of the data contained in the signal EQ_(OUT) is determined from the signal THCP₁ through the signal THCP₃ outputted by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, respectively. For example, when the signal THCP₁ through the signal THCP₃ outputted by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, respectively, are all “1”, the level of the data included in the signal EQ_(OUT) is determined as the fourth data level DL₁. When the signal THCP₁ and the signal THCP₂ outputted by the first threshold voltage comparator 112-1 and the second threshold voltage comparator 112-2, respectively, are both “1”, and the signal THCP₃ outputted by the third threshold voltage comparator 112-3 is “0”, the level of the data included in the signal EQ_(OUT) is determined as the third data level DL₃. When the signal THCP₁ outputted by the first threshold voltage comparator 112-1 is “1”, and the signal THCP₂ and the signal THCP₃ outputted by the second threshold voltage comparator 112-2 and the third threshold voltage comparator 112-3, respectively, are both “0”, the level of the data included in the signal EQ_(OUT) is determined as the second data level DL₂. When the signal THCP₁ through the signal THCP₃ outputted by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, respectively, are all “0”, the level of the data included in the signal EQ_(OUT) is determined as the first data level DL₁. Therefore, the level of the data included in the signal EQ_(OUT) may be determined by checking the values outputted by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3.

The first data level comparator 114-1 through the fourth data level comparator 114-4 compare the level of the data included in the signal EQ_(OUT) with the first reference data level DLR₁ through the fourth reference data level DLR₄, respectively, and output the comparison result thereof.

For example, the first data level comparator 114-1 compares the signal EQ_(OUT) with the first reference data level DLR₁ for each clock CLK, and outputs a signal DLCP₁ representing the comparison result. Specifically, the first data level comparator 114-1 outputs DLCP₁=1 when the level of the data included in the signal EQ_(OUT) is greater than the first reference data level DLR₁, and outputs DLCP₁=0 when the level of the data included in the signal EQ_(OUT) is smaller than the first reference data level DLR₁.

The second data level comparator 114-2 compares the signal EQ_(OUT) with the second reference data level DLR₂ for each clock CLK, and outputs a signal DLCP₂ representing the comparison result. Specifically, the second data level comparator 114-2 outputs DLCP₂=1 when the level of the data included in the signal EQ_(OUT) is greater than the second reference data level DLR₂, and outputs DLCP₂=0 when the level of the data included in the signal EQ_(OUT) is smaller than the second reference data level DLR₂.

The third data level comparator 114-3 compares the signal EQ_(OUT) with the third reference data level DLR₃ for each clock CLK, and outputs a signal DLCP₃ representing the comparison result. Specifically, the third data level comparator 114-3 outputs DLCP₃=1 when the level of the data included in the signal EQ_(OUT) is greater than the third reference data level DLR₃, and outputs DLCP₃=0 when the level of the data included in the signal EQ_(OUT) is smaller than the third reference data level DLR₃.

The fourth data level comparator 114-4 compares the signal EQ_(OUT) with the fourth reference data level DLR₄ for each clock CLK, and outputs a signal DLCP₄ representing the comparison result. Specifically, the fourth data level comparator 114-4 outputs DLCP₄=1 when the level of the data included in the signal EQ_(OUT) is greater than the fourth reference data level DLR₄, and outputs DLCP₄=0 when the level of the data included in the signal EQ_(OUT) is smaller than the fourth reference data level DLR₄.

In other words, each of the first data level comparator 114-1 through the fourth data level comparator 114-4 compare the level of the data included in the signal EQ_(OUT) with the corresponding reference data level thereof.

The signal DLCP₁ through the signal DLCP₄ outputted by the first data level comparator 114-1 through the fourth data level comparator 114-4, respectively, are used to determined which one of the level of the data included in the signal EQ_(OUT) and the reference data level is greater.

For example, when the level of the data included in the signal EQ_(OUT) is determined to be the first data level DL₁ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₁ outputted by the first data level comparator 114-1 is “0”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be smaller than the first reference data level DLR₁. Similarly, when the level of the data included in the signal EQ_(OUT) is determined to be the first data level DL₁ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₁ outputted by the fourth data level comparator 114-1 is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the first reference data level DLR₁.

When the level of the data included in the signal EQ_(OUT) is determined to be the second data level DL₂ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₂ outputted by the second data level comparator 114-2 is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the second reference data level DLR₂.

In another example, when the level of the data included in the signal EQ_(OUT) is determined to be the fourth data level DL₄ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₄ outputted by the fourth data level comparator 114-4 is “1”, the level of the data included in the signal EQ_(OUT) is deduced or determined to be greater than the fourth reference data level DLR₄.

The sampler 110 a outputs the output signals SMPL_(OUT) containing the signal THCP₁ through the signal THCP₃ outputted by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, respectively, and the signal DLCP₁ through the signal DLCP₄ outputted by the first data level comparator 114-1 through the fourth data level comparator 114-4, respectively.

The output signal SMPL_(OUT) is transmitted to the controller 130 via the DEMUX 120 as a signal DATA_(OUT).

The controller 130, upon receiving the output signal SMPL_(OUT), updates the threshold voltages and the reference data levels according to the signals THCP₁ through the signal THCP₃ and the signal DLCP₁ through the signal DLCP₄ included in the output signal SMPL_(OUT).

Specifically, the reference data level controller 134 adjusts the first reference data level DLR₁ through the fourth reference data level DLR₄ based on the signal DLCP₁ through the signal DLCP₄ outputted by the first data level comparator 114-1 through the fourth data level comparator 114-4, respectively, and included in the output signal SMPL_(OUT).

More specifically, for example, when the level of the data included in the signal EQ_(OUT) is determined as the first data level DL₁ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₁ outputted from the first data level comparator 114-1 is “0”, the reference data level controller 134 decreases the first reference data level DLR₁ by a predetermined value to generate the first updated reference data level DLUR₁. When the level of the data included in the signal EQ_(OUT) is determined as the first data level DL₁ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₁ outputted from the first data level comparator 114-1 is “1”, the reference data level controller 134 increases the first reference data level DLR₁ by a predetermined value to generate the first updated reference data level DLUR₁.

Similarly, for example, when the level of the data included in the signal EQ_(OUT) is determined as the second data level DL₂ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₂ outputted from the second data level comparator 114-2 is “0”, the reference data level controller 134 decreases the second reference data level DLR₂ by a predetermined value to generate the second updated reference data level DLUR₂. When the level of the data included in the signal EQ_(OUT) is determined as the second data level DL₂ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₂ outputted from the second data level comparator 114-2 is “1”, the reference data level controller 134 increases the second reference data level DLR₂ by a predetermined value to generate the second updated reference data level DLUR₂.

As another example, when the level of the data included in the signal EQ_(OUT) is determined as the third data level DL₃ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₃ outputted from the third data level comparator 114-3 is “0”, the reference data level controller 134 decreases the third reference data level DLR₃ by a predetermined value to generate the third updated reference data level DLUR₃. When the level of the data included in the signal EQ_(OUT) is determined as the third data level DL₃ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₃ outputted from the third data level comparator 114-3 is “1”, the reference data level controller 134 increases the third reference data level DLR₃ by a predetermined value to generate the third updated reference data level DLUR₃.

As yet another example, when the level of the data included in the signal EQ_(OUT) is determined as the fourth data level DL₄ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₄ outputted from the fourth data level comparator 114-4 is “0”, the reference data level controller 134 decreases the fourth reference data level DLR₄ by a predetermined value to generate the fourth updated reference data level DLUR₄. When the level of the data included in the signal EQ_(OUT) is determined as the fourth data level DL₄ by the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3, and the signal DLCP₄ outputted from the fourth data level comparator 114-4 is “1”, the reference data level controller 134 increases the fourth reference data level DLR₄ by a predetermined value to generate the fourth updated reference data level DLUR₄.

Threshold voltage controller 132 calculates the first updated threshold voltage VUTH₁ through the third updated threshold voltage VUTH₃ from the first updated reference data level DLUR₁ through the fourth updated reference data level DLUR₄ generated by the reference data level controller 134.

For example, when the third reference data level DLR₃ is updated with the third updated reference data level DLUR₃, the second updated threshold voltage VUTH₂ may be calculated from equation 6 below. That is, when the third updated reference data level DLUR₃ is generated by updating the third reference data level DLR₃, the second threshold voltage VTH₂ may also be updated with the second updated threshold voltage VUTH₂ which is an average value of the second reference data level DLR₂ and the third updated reference data level DLUR₃ according to the equation 6 below.

$\begin{matrix} {{VUTH}_{2} = \frac{{DLUR}_{3} + {DLR}_{2}}{2}} & \left\lbrack {{Equation}6} \right\rbrack \end{matrix}$

In addition, when the third updated reference data level DLUR₃ is generated to update the reference data level DLR₃, the third threshold voltage VTH₃ may be updated with the third updated threshold voltage VUTH₃ which is an average value of the fourth reference data level DLR₄ and the third updated reference data level DLUR₃ according to equation 7 below.

$\begin{matrix} {{VUTH}_{3} = \frac{{DLR}_{4} + {DLUR}_{3}}{2}} & \left\lbrack {{Equation}7} \right\rbrack \end{matrix}$

That is, the threshold voltage controller 132 may update only the second threshold voltage VTH₂ from the third updated reference data level DLUR₃, update only the third threshold voltage VTH₃, or update both the second threshold voltage VTH₂ and the third threshold voltage VTH₃.

Similarly, when the second updated reference data level DLUR₂ is generated, and the second reference data level DLR₂ is updated, the first threshold voltage VTH₁ may be updated with the first updated threshold voltage VUTH₁ which is an average value of the first reference data level DLR₁ and the second updated reference data level DLUR₂ according to the equation 8 below.

$\begin{matrix} {{VUTH}_{1} = \frac{{DLUR}_{2} + {DLR}_{1}}{2}} & \left\lbrack {{Equation}8} \right\rbrack \end{matrix}$

In addition, when the second updated reference data level DLUR₂ is generated and the reference data level DLR₂ is updated, the second threshold voltage VTH₂ may be updated with the second updated threshold voltage VUTH₂ which is an average value of the third reference data level DLR₃ and the second updated reference data level DLUR₂ according to the equation 9 below.

$\begin{matrix} {{VUTH}_{2} = \frac{{DLR}_{3} + {DLUR}_{2}}{2}} & \left\lbrack {{Equation}9} \right\rbrack \end{matrix}$

That is, the threshold voltage controller 132 may update only the first threshold voltage VTH₁ from the second updated reference data level DLUR₂, update only the second threshold voltage VTH₂, or update both the first threshold voltage VTH₁ and the second threshold voltage VTH₂.

However, when the first updated reference data level DLUR₁ is generated by adjusting the first reference data level DLR₁, only the first threshold voltage VTH₁ is updated as shown in equation 10 below, and when the fourth reference data level DLUR₁ is generated by adjusting the fourth reference data level DLR₁, only the third threshold voltage VTH₃ is updated as in equation 11 below.

$\begin{matrix} {{VUTH}_{1} = \frac{{DLR}_{2} + {DLUR}_{1}}{2}} & \left\lbrack {{Equation}10} \right\rbrack \end{matrix}$ $\begin{matrix} {{VUTH}_{3} = \frac{{DLUR}_{4} + {DLR}_{3}}{2}} & \left\lbrack {{Equation}11} \right\rbrack \end{matrix}$

The controller 130 provides the first updated reference data level DLUR₁ through the third updated reference data level DLUR₃ and the first updated threshold voltage VUTH₁ through the third updated threshold voltage VUTH₃ to the sampler 110 a.

Hereinafter, the PAM-4 receiver according to the present invention will be described in more detail with reference to FIGS. 8B through 8F.

In order to facilitate description, it is assumed that the PAM-4 receiver according to the present invention sequentially receives data “10”, “01”, “10” and “00”.

The received data “10” is equalized by the equalizer 100 and outputted as the equalized signal EQ_(OUT), and the signal EQ_(OUT) is inputted to the sampler 110 a.

As shown in FIG. 8B, the signal EQ_(OUT) is inputted into the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 and also into the first data level comparator 114-1 through the fourth data level comparator 114-4, and is compared therewith. That is, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 compare the level of the data corresponding to the data “10” included in the signal EQ_(OUT) with the first threshold voltage VTH₁ through the third threshold voltage VTH₃, and the first data level comparator 114-1 through the fourth data level comparator 114-4 compare the level of the data corresponding to the data “10” included in the signal EQ_(OUT) with the first reference data level DLR₁ through the fourth reference data level DLR₄.

Since the level of the data included in the signal EQ_(OUT) corresponds to data “10”, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 should determine the level as the third data level DL₃. In addition, the third data level comparator 114-3 outputs DLCP₃=0 or DLCP₃=1 according to the result of comparison between the level of the data included in the signal EQ_(OUT) and the third reference data level DLR₃. That is, the third data level comparator 114-3 outputs DLCP₃=0 or DLCP₃=1 depending on which one of the level of the data included in the signal EQ_(OUT) and the third reference data level DLR₃ is greater.

The comparison result is transmitted to the controller 130. The controller 130 increases or decreases the third reference data level DLR₃ according to the value of DLCP₃ to generate an third updated reference data level DLUR₃, and generates a second updated threshold voltage VUTH₂ and a third updated threshold voltage VUTH₃ according to the equations 6 and 7.

The third updated reference data level DLUR₃, the second updated threshold voltage VUTH₂ and the third updated threshold voltage VUTH₃ are transmitted to the sampler 110 a.

Once the third updated reference data level DLUR₃, the second updated threshold voltage VUTH₂ and the third updated threshold voltage VUTH₃ are received, the sampler 110 a performs a comparison of the next data “01” as shown in FIG. 8C.

Specifically, the received data “01” is equalized by the equalizer 100 and outputted as an equalized signal EQ_(OUT), which is then inputted to the sampler 110 a.

As shown in FIG. 8C, the signal EQ_(OUT) is inputted into the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 and also into the first data level comparator 114-1 through the fourth data level comparator 114-4, and is compared therewith. That is, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 compare the level of the data corresponding to the data “01” included in the signal EQ_(OUT) with the first threshold voltage VTH₁, the second updated threshold voltage VUTH₂ and the third updated threshold voltage VUTH₃, and the first data level comparator 114-1 through the fourth data level comparator 114-4 compare the level of the data corresponding to the data “01” included in the signal EQ_(OUT) with the first reference data level DLR₁, the second reference data level DLR₂, the third updated reference data level DLUR₃ and the fourth reference data level DLR₄.

Since the level of the data included in the signal EQ_(OUT) corresponds to data “01”, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 should determine the level as the second data level DL₂. In addition, the second data level comparator 114-2 outputs DLCP₂=0 or DLCP₂=1 according to the result of comparison between the level of the data included in the signal EQ_(OUT) and the second reference data level DLR₂. That is, the second data level comparator 114-2 outputs DLCP₂=0 or DLCP₂=1 depending on which one of the level of the data included in the signal EQ_(OUT) and the second reference data level DLR₂ is greater.

The comparison result is transmitted to the controller 130. The controller 130 increases or decreases the second reference data level DLR₂ according to the value of DLCP₂ to generate an second updated reference data level DLUR₂, and generates a first updated threshold voltage VUTH₁ and a second re-updated threshold voltage VU2TH₂ according to the equations 12 and 13.

$\begin{matrix} {{VUTH}_{1} = \frac{{DLUR}_{2} + {DLR}_{1}}{2}} & \left\lbrack {{Equation}12} \right\rbrack \end{matrix}$ $\begin{matrix} {{{VU}2{TH}_{2}} = \frac{{DLUR}_{3} + {DLUR}_{2}}{2}} & \left\lbrack {{Equation}13} \right\rbrack \end{matrix}$

In the case of equation 13, since the third updated reference data level DLUR₃ is generated by receiving data “10”, and the second updated reference data level DLUR₂ is generated by receiving data “01”, the second re-updated threshold voltage VU2TH₂ is calculated from the average of the third updated reference data level DLUR₃ and the second updated reference data level DLUR₂.

The second updated reference data level DLUR₂, the first updated threshold voltage VUTH₁ and the second re-updated threshold voltage VU2TH₂ are transmitted to the sampler 110 a.

Once the second updated reference data level DLUR₂, the first updated threshold voltage VUTH₁ and the second re-updated threshold voltage VU2TH₂ are received, the sampler 110 a performs a comparison of the next data “10” as shown in FIG. 8D.

Specifically, the received data “10” is equalized by the equalizer 100 and outputted as an equalized signal EQ_(OUT), which is then inputted to the sampler 110 a.

As shown in FIG. 8C, the signal EQ_(OUT) is inputted into the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 and also into the first data level comparator 114-1 through the fourth data level comparator 114-4, and is compared therewith. That is, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 compare the level of the data corresponding to the data “01” included in the signal EQ_(OUT) with the first updated threshold voltage VUTH₁, the second re-updated threshold voltage VU2TH₂ and the third updated threshold voltage VUTH₃, and the first data level comparator 114-1 through the fourth data level comparator 114-4 compare the level of the data corresponding to the data “01” included in the signal EQ_(OUT) with the first reference data level DLR₁, the second updated reference data level DLUR₂, the third updated reference data level DLUR₃ and the fourth reference data level DLR₄.

Since the level of the data included in the signal EQ_(OUT) corresponds to data “10”, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 should determine the level as the third data level DL₃. In addition, the third data level comparator 114-3 outputs DLCP₃=0 or DLCP₃=1 according to the result of comparison between the level of the data included in the signal EQ_(OUT) and the third updated reference data level DLUR₃. That is, the third data level comparator 114-3 outputs DLCP₃=0 or DLCP₃=1 depending on which one of the level of the data included in the signal EQ_(OUT) and the third updated reference data level DLUR₃ is greater.

Here, when the reference data level is updated by the previous data, the reference data level compared with the current data included in the signal EQ_(OUT) is always the updated (or re-updated) reference data level.

The comparison result is transmitted to the controller 130. The controller 130 increases or decreases the third updated reference data level DLUR₃ according to the value of DLCP₃ to generate a third re-updated reference data level DLU2R3, and generates a second re-re-updated threshold voltage VU3TH₂ and a third re-updated threshold voltage VU2TH₃ according to the equations 12 and 13 below, respectively.

$\begin{matrix} {{{VU}3{TH}_{2}} = \frac{{{DLU}2R_{3}} + {DLUR}_{2}}{2}} & \left\lbrack {{Equation}14} \right\rbrack \end{matrix}$ $\begin{matrix} {{{VU}2{TH}_{3}} = \frac{{DLR}_{4} + {{DLU}2R_{3}}}{2}} & \left\lbrack {{Equation}15} \right\rbrack \end{matrix}$

A third re-updated reference data level DLU2R₃, a second re-re-updated threshold voltage VU3TH₂, and a third re-updated threshold voltage VU2T₃ are transmitted to the sampler 110 a.

Once the third re-updated reference data level DLU2R₃, the second re-re-updated threshold voltage VU3TH₂ and the third re-updated threshold voltage VU2TH₃ are received, the sampler 110 a performs a comparison of the next data “00” as shown in FIG. 8E.

Specifically, the received data “00” is equalized by the equalizer 100 and outputted as an equalized signal EQ_(OUT), which is then inputted to the sampler 110 a.

As shown in FIG. 8E, the signal EQ_(OUT) is inputted into the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 and also into the first data level comparator 114-1 through the fourth data level comparator 114-4, and is compared therewith. That is, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 compare the level of the data corresponding to the data “00” included in the signal EQ_(OUT) with the first updated threshold voltage VUTH₁, the second re-re-updated threshold voltage VU3TH₂ and the third re-updated threshold voltage VU2TH₃, and the first data level comparator 114-1 through the fourth data level comparator 114-4 compare the level of the data corresponding to the data “00” included in the signal EQ_(OUT) with the first reference data level DLR₁, the second updated reference data level DLUR₂, the third re-updated reference data level DLU2R₃ and the fourth reference data level DLR₄.

Since the level of the data included in the signal EQ_(OUT) corresponds to data “00”, the first threshold voltage comparator 112-1 through the third threshold voltage comparator 112-3 should determine the level as the first data level DL₁. In addition, the first data level comparator 114-1 outputs DLCP₁=0 or DLCP₁=1 according to the result of comparison between the level of the data included in the signal EQ_(OUT) and the first reference data level DLR₁. That is, the first data level comparator 114-1 outputs DLCP₁=0 or DLCP₁=1 depending on which one of the level of the data included in the signal EQ_(OUT) and the first reference data level DLR₁ is greater.

The comparison result is transmitted to the controller 130. The controller 130 increases or decreases the first reference data level DLR₁ according to the value of DLCP₁ to generate an first updated reference data level DLUR₁, and generates a first re-updated threshold voltage VU2TH₁ according to the equation 16 below.

$\begin{matrix} {{{VU}2{TH}_{1}} = \frac{{DLUR}_{2} + {DLUR}_{1}}{2}} & \left\lbrack {{Equation}16} \right\rbrack \end{matrix}$

The first updated reference data level DLUR₁ and the first re-updated threshold voltage VU2TH₁ are transmitted to the sampler 110 a.

Once the first updated reference data level DLUR₁ and the first re-updated threshold voltage VU2TH₁ are received, the sampler 110 a performs a comparison of the next data as shown in FIG. 8F, and the controller updates the reference data level and the threshold voltage.

Hereinafter, a method of adaptively adjusting threshold voltages of a PAM-N receiver according to an embodiment of the present invention will be described in detail.

FIG. 10 is a flowchart illustrating a method of adaptively adjusting threshold voltages of a PAM-N receiver according to an embodiment of the present invention. The method of adaptively adjusting threshold voltages of a PAM-N receiver according to an embodiment of the present invention is performed in the PAM-N receiver shown in FIG. 6 , and as described above, the level of the data included in the received signal RS or the equalized signal EQ_(OUT) is one of the first data level DL₁ through the N^(th) data level DL_(N).

Hereinafter, any one data level selected from the first data level DL₁ through the N^(th) data level DL_(N) is referred to as “K^(th) data level DL_(K)” and the data level which is one level lower than the K^(th) data level DL_(K) is referred to as “(K−1)^(th) data level DL_((K−1))” as described above with reference to FIGS. 5 and 6 .

Referring to FIG. 10 , the sampler 110 compares the level of the data included in the equalized signal EQ_(OUT) with the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)) to determine the data level (S100).

Specifically, as described above with reference to FIG. 7A, the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1) of the sampler 110 compare the level of each data included in the signal EQ_(OUT) with the first threshold voltage VTH₁ through the (N−1)^(th) threshold voltage VTH_((N−1)), and the comparison result is outputted.

For example, the first threshold voltage comparator 112-1 compares the signal EQ_(OUT) with the first threshold voltage VTH₁ for each clock CLK and outputs a signal THCP₁ representing a comparison result. That is, the first threshold voltage comparator 112-1 outputs THCP₁=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the first threshold voltage VTH₁, and outputs THCP₁=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the first threshold voltage VTH₁.

The second threshold voltage comparator 112-2 compares the signal EQ_(OUT) with the second threshold voltage VTH₂ for each clock CLK and outputs a signal THCP₂ representing a comparison result. That is, the second threshold voltage comparator 112-2 outputs THCP₂=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the second threshold voltage VTH₂, and outputs THCP₂=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the second threshold voltage VTH₂.

Similarly, the (N−2)^(th) threshold voltage comparator 112-(N−2) compares the signal EQ_(OUT) with the (N−2)^(th) threshold voltage VTH_((N−2)) for each clock CLK and outputs a signal THCP_((N−2)) representing a comparison result. That is, the (N−2)^(th) threshold voltage comparator 112-(N−2) outputs THCP_((N−2))=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the (N−2)^(th) threshold voltage VTH_((N−2)), and outputs THCP_((N−2))=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the (N−2)^(th) threshold voltage VTH_((N−2)).

Similarly, the (N−1)^(th) threshold voltage comparator 112-(N−1) compares the signal EQ_(OUT) with the (N−1)^(th) threshold voltage VTH_((N−1)) for each clock CLK and outputs a signal THCP_((N−1)) representing a comparison result. That is, the (N−1)^(th) threshold voltage comparator 112-(N−1) outputs THCP_((N−1))=1 for each data when the level of the data included in the signal EQ_(OUT) is greater than the (N−1)^(th) threshold voltage VTH_((N−1)), and outputs THCP_((N−1))=0 for each data when the level of the data included in the signal EQ_(OUT) is smaller than the (N−1)^(th) threshold voltage VTH_((N−1)).

Thereafter, the sampler 110 compares the level of the data determined to have the K^(th) data level DL_(K) in step S100 with the K^(th) reference data level DLR_(K) (S200).

Specifically, when a data is determined to have a level of the K^(th) data level DL_(K) in step S100, the level of this data is compared with the K^(th) reference data level DLR_(K) to determine which one of the level of this data and the K^(th) reference data level DLR_(K) is greater. Here, the K^(th) reference data level DLR_(K) represents one of the first reference data level DLR₁ through the N^(th) reference data level DLR_(N), and as described above, the comparison may be performed for each natural number K satisfying 1≤K≤N.

For example, when a data is determined to have a level of the first data level DL₁ in step S100 (i.e. K=1), the level of this data is compared with the first reference data level DLR₁ to determine which one of the level of this data and the first reference data level DLR₁ is greater. Similarly, when a data is determined to have a level of the fifth data level DL₅ in step S100 (i.e. K=5), the level of this data is compared with the fifth reference data level DLR₅ to determine which one of the level of this data and the fifth reference data level DLR₅ is greater. When a data is determined to have a level of the N^(th) data level DL_(N) in step S100 (i.e. K=N), the level of this data is compared with the N^(th) reference data level DLR_(N) to determine which one of the level of this data and the N^(th) reference data level DLR_(N) is greater.

Thereafter, the controller 130 increases the K^(th) reference data level DLR_(K) when [DL_(K)>DLR_(K)] or decreases the K^(th) reference data level DLR_(K) when [DL_(K)<DLR_(K)] according to the comparison result obtained in step S200 to generate a K^(th) updated reference data level DLUR_(K), and the K^(th) reference data level DLR_(K) is updated with the K^(th) updated (replaced) reference data level DLUR_(K) (S300).

Specifically, when the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted by the K^(th) data level comparator 114-K is “1” (i.e. DL_(K)>DLR_(K) as shown in FIG. 9A), the reference data level controller 134 increases the K^(th) reference data level DLR_(K) by a predetermined voltage to generate the K^(th) updated reference data level DLUR_(K).

In addition, for example, when the data included in the signal EQ_(OUT) is determined to have a level of the K^(th) data level DL_(K) by the first threshold voltage comparator 112-1 through the (N−1)^(th) threshold voltage comparator 112-(N−1), and the signal DLCP_(K) outputted by the K^(th) data level comparator 114-K is “0” (i.e. DL_(K)<DLR_(K) as shown in FIG. 9B), the reference data level controller 134 decreases the K^(th) reference data level DLR_(K) by a predetermined voltage to generate the K^(th) updated reference data level DLUR_(K).

Thereafter, the controller 130 updates at least one of (K−1)^(th) threshold voltage VTH_((K−1)) and K^(th) threshold voltage VTH_(K) with (K−1)^(th) updated threshold voltage VUTH_((K−1)) and K^(th) updated threshold voltage VUTH_(K) by calculating at least one of the (K−1)^(th) updated threshold voltage VUTH_((K−1)) and the K^(th) updated threshold voltage VUTH_(K) from the K^(th) updated reference data level DLUR_(K) generated in S300 (S400).

Hereinafter, step S400 will be described in detail with reference to FIG. 11 .

FIG. 11 is a flowchart illustrating in detail step S400 including steps S410 through S440.

Referring to FIG. 11 , as in the equation 4 above, the (K−1)^(th) updated threshold voltage VUTH_((K−1)) is calculated from the average of the (K−1)^(th) reference data level DLR_((K−1)) and the K^(th) updated reference data level DLUR_(K) (S410).

Thereafter, the (K−1)^(th) threshold voltage VTH_((K−1)) is updated with the (K−1)^(th) updated threshold voltage VUTH_((K−1)) (S420).

Thereafter, as in the equation 5 above, the K^(th) updated threshold voltage VUTH_(K) is calculated from the average of the (K+1)^(th) reference data level DLR_((K+1)) and the K^(th) updated reference data level DLUR_(K) (S430).

Thereafter, the K^(th) threshold voltage VTH_(K) is updated with the K^(th) updated threshold voltage VUTH_(K) (S440).

According to an embodiment of the present invention, only steps S410 and S420, only steps S430 and S440, or all of steps S410 through S440 may be performed.

In one embodiment, when the first reference data level DLR₁ is adjusted to generate the first updated reference data level DLUR₁, only the first threshold voltage VTH₁ may be updated (that is, only the steps S430 and S440 are performed), and when the N^(th) reference data level DLR_(N) is adjusted to generate the N^(th) updated reference data level DLUR_(N), only the (N−1)^(th) threshold voltage VTH_((N−1)) may be updated (that is, only the steps S410 and S420 are performed). In another embodiment, when any one of the second reference data level DLR₂ through the (N−1)^(th) reference data level DLR_((N−1)) is adjusted, only the steps S410 and S420 may be performed, only the steps S430 and S440 may be performed, or all of the steps S410 through S440 may be performed.

Referring back to FIG. 10 , when the received signal RS or the equalized signal EQ_(OUT) is a differential signal, the (N−K+1)^(th) threshold voltage VTH_((N−K+1)) of the sampler 110 may be updated with a (N−K+1)^(th) updated threshold voltage VUTH_((N−K+1)) which is obtained by inverting the (K−1)^(th) updated threshold voltage VUTH_((K−1)) (S500).

As described above, since the differential signal includes a differential pair consisting of non-inverted and inverted signals, a threshold voltage for the non-inverted signal may be inverted to obtain a threshold voltage for the inverted signal. Therefore, all of the first updated threshold voltage VUTH₁ through the (N−1)^(th) updated threshold voltage VUTH_((N−1)) are not required to be calculated.

The received signal RS or the equalized signal EQ_(OUT) includes a plurality of data, and by repeatedly performing the steps S100 through S500 for each of the plurality of data, the threshold voltage and the reference data level may be repeatedly updated (S600).

The PAM-N receiver and the threshold voltage control method according to the present invention have the following advantages.

(1) Since the threshold voltages are adaptively adjusted according to the level of the data included in the received signal, threshold voltages optimized for the received signal may be obtained.

(2) Since the value of the received data is determined using the threshold voltages which have been subjected to optimization, the value of the received data may be determined accurately. 

What is claimed is:
 1. A method of adjusting threshold voltages of a PAM-N receiver comprising a sampler comparing a level of data contained in an equalized signal EQOUT with first reference data level DLR1 through Nth reference data level DLRN and first threshold voltage VTH1 through (N−1)th threshold voltage VTH(N−1), the method comprising: (a) determining the level of the data by comparing the data in the equalized signal EQ_(OUT) with the first threshold voltage VTH1 through the (N−1)th threshold voltage VTH(N−1); (b) comparing the level of the data determined in (a) as Kth data level DLK with Kth reference data level DLRK; (c) increasing the Kth reference data level DLRK when DLK is greater than DLRK according to comparison result obtained in (b) and decreasing the Kth reference data level DLRK when DLK is smaller than DLRK according to the comparison result obtained in (b) to generate Kth updated reference data level DLURK; and (d) updating at least one of (K−1)th threshold voltage VTH(K−1) and Kth threshold voltage VTHK with (K−1)th updated threshold voltage VUTH(K−1) and Kth updated threshold voltage VUTHK by calculating at least one of the (K−1)th updated threshold voltage VUTH(K−1) and the Kth updated threshold voltage VUTHK from the Kth updated reference data level DLURK (where N is a natural number equal to or greater than 2, K is a natural number satisfying 1≤K≤N, DLK is one of DL1 through DLN satisfying DL1<DL2<. . .<DL(N-1)<DLN, DLRK is one of DLR1 through DLRN satisfying DLR1<DLR2<. . .<DLR(N−1)<DLRN, VTH(K−1) is one of VTH1 through VTH(N−1) satisfying VTH1<VTH2<. . .<VTH(N−2)<VTH(N−1)).
 2. The method of claim 1, further comprising: (e) updating (N−K+1)th threshold voltage VTH(N−K+1) with (N−K+1)th updated threshold voltage VUTH(N−K−1) obtained by inverting the (K−1)th updated threshold voltage VUTH(K−1) when the equalized signal EQOUT is a differential signal (where, K is a natural number satisfying N/2+1<K≤N).
 3. The method of claim 1, wherein (d) comprises: (d-1) calculating the (K−1)th updated threshold voltage VUTH(K−1) from an average of (K-1)th reference data level DLR(K−1) and the Kth updated reference data level DLURK; and (d-2) updating the (K−1)th threshold voltage VTH(K−1) with the (K−1)th updated threshold voltage VUTH(K-1).
 4. The method of claim 1, wherein (d) comprises: (d-3) calculating the Kth updated threshold voltage VUTHK from an average of (K+1)th reference data level DLR(K+1) and the Kth updated reference data level DLURK; and (d-4) updating the Kth threshold voltage VTHK with the Kth updated threshold voltage VUTHK.
 5. The method of claim 1, wherein (d) comprises: (d-1) calculating the (K−1)th updated threshold voltage VUTH(K−1) from an average of (K-1)th reference data level DLR(K−1) and the Kth updated reference data level DLURK; (d-2) updating the (K−1)th threshold voltage VTH(K−1) with the (K−1)th updated threshold voltage VUTH(K−1); (d-3) calculating the Kth updated threshold voltage VUTHK from an average of (K+1)th reference data level DLR(K+1) and the Kth updated reference data level DLURK; and (d-4) updating the Kth threshold voltage VTHK with the Kth updated threshold voltage VUTHK.
 6. The method of claim 1, further comprising: (h) performing, when the received signal contains a plurality of data, (a) through (d) for each of the plurality of data.
 7. A PAM-N receiver comprising: an equalizer generating an equalized signal EQOUT containing data having at least one of first data level DL1 through Nth data level DLN obtained by equalizing a received signal; a sampler determining a level of the data by comparing the data in the equalized signal EQ_(OUT) with first reference data level DLR1 through Nth reference data level DLRN and first threshold voltage VTH1 through (N−1)th threshold voltage VTH(N−1); and a controller adjusting the first reference data level DLR1 through the Nth reference data level DLRN and the first threshold voltage VTH1 through the (N−1)th threshold voltage VTH(N−1) according to an output signal SMPLOUT indicating a result of comparison performed by the sampler; wherein the sampler comprises a Kth data level comparator outputting: “1” as the output signal SMPLOUT when DLK is greater than DLRK; and “0” as the output signal SMPLOUT when DLK is smaller than DLRK by comparing the level of the data determined to have Kth data level DLK with Kth reference data level DLRK; and wherein the controller comprises: a reference data level controller generating an Kth updated reference data level DLURK obtained by increasing the Kth reference data level DLRK when an output of the Kth data level comparator is “1” and by decreasing the Kth reference data level DLRK when the output of the Kth data level comparator is “0”; and a threshold voltage controller updating at least one of (K−1)th threshold voltage VTH(K−1) and Kth threshold voltage VTHK with (K-1)th updated threshold voltage VUTH(K−1) and Kth updated threshold voltage VUTHK by calculating at least one of the (K−1)th updated threshold voltage VUTH(K−1) and the Kth updated threshold voltage VUTHK from the Kth updated reference data level DLURK (where N is a natural number equal to or greater than 2, K is a natural number satisfying 1≤K≤N, DLK is one of DL1 through DLN satisfying DL1<DL2<. . .<DL(N−1)<DLN, DLRK is one of DLR1 through DLRN satisfying DLR1<DLR2<. . .<DLR(N−1)<DLRN, VTH(K−1) is one of VTH1 through VTH(N−1) satisfying VTH1<VTH2<. . .<VTH(N−2)<VTH(N−1)).
 8. The PAM-N receiver of claim 7, wherein the threshold voltage controller updates (N−K+1)th threshold voltage VTH(N−K+1) with (N−K+1)th updated threshold voltage VUTH(N−K+1) obtained by inverting the (K−1)th updated threshold voltage VUTH(K−1) when the equalized signal EQOUT is a differential signal (where, K is a natural number satisfying N/2+1<K≤A).
 9. The PAM-N receiver of claim 7, wherein the threshold voltage controller: calculates the (K−1)th updated threshold voltage VUTH(K−1) from an average of (K−1)th reference data level DLR(K−1) and the Kth updated reference data level DLURK; and updates the (K−1)th threshold voltage VTH(K−1) with the (K−1)th updated threshold voltage VUTH(K−1).
 10. The PAM-N receiver of claim 7, wherein the threshold voltage controller: calculates the Kth updated threshold voltage VUTHK from an average of (K+1)th reference data level DLR(K+1) and the Kth updated reference data level DLURK; and updates the Kth threshold voltage VTHK with the Kth updated threshold voltage VUTHK. 